As high-speed performance and high integration of semiconductor devices becomes more important, research regarding the use of copper metal lines is becoming more common. Copper has higher electromigration resistance and lower bulk resistivity than the aluminum or aluminum alloy that is often used as a material for metallization in a related art semiconductor device.
When used in a semiconductor device, copper lines are typically formed using a damascene process.
The damascene process generally includes forming a trench, filling copper into the trench by electrochemical plating (ECP), and removing overfilled copper by chemical mechanical polishing (CMP).
Since ECP typically provides better bottom-up gapfill capability than a physical vapor deposition (PVD) or a chemical vapor deposition (CVD), ECP is often used to form copper lines.
As the technology of semiconductor devices continues to advance, the desired width of gates becomes smaller and finer patterns are required.
Accordingly, copper lines in semiconductor devices are also becoming smaller, leading to voids or seams in via holes and trenches for small-sized copper lines. Thus, a need exists in the art for a metal line of a semiconductor device and fabricating method thereof which includes copper lines formed without voids or seams.